1. Field of the Invention
The present invention relates to an encoding method and apparatus for block segmenting a digital video signal, in particular, to an encoding method and apparatus suitable for a digital VTR.
2. Description of the Prior Art
Digital VTRs that record digital video signals on magnetic tapes with rotating heads are known. A digital VTR encodes an input video signal so as to compress the data amount thereof. For example, as a prior art reference, a block encoding technique where a video signal is formed of two-dimensional blocks and encoded block by block is known. The applicant of the present invention has proposed an ADRC (Adaptive Dynamic Range Coding) system. In the ADRC system, video data is converted into block-structured data. Each pixel data of each block is quantized with a quantizing step width corresponding to a dynamic range of the block. This system is disclosed as U.S. Pat. No. 4,703,352.
In analog VTRs, it is known that even if dubbing is repeated (multiple debugging is performed), the quality of a dubbed image is deteriorated. However, in digital VTRs, even if the multiple dubbing is repeated, the image quality is not deteriorated. To accomplish the multiple dubbing without deterioration of the image quality in the digital VTRs, when block codes are repeatedly encoded and decoded, the boundary of each block should not be moved. However, as will be described, it was difficult to satisfy such conditions.
FIG. 5 is a block diagram schematically showing an example of a dubbing system. In the drawing, reference numerals 1A and 1B are digital VTRs. The digital VTR 1A has an analog video input terminal 1Aa, a digital video input terminal 1Da, an analog video output terminal OAa, and a digital video output terminal ODa. Likewise, the digital VTR 1B has input terminals lab and 1Db and output terminals OAb and ODb.
An A/D converter 2 is disposed between the input terminal 1Aa and a record processing circuit 3. The A/D converter 2 converts an input analog video signal into a digital video signal of for example 8 bits/sample. The output signal of the A/D converter 2 is supplied to the record processing circuit 3. The record processing circuit 3 performs various predetermined processes such as block segmenting process, block encoding process, error correction code encoding process, frame segmenting process, and channel modulating process. The record processing circuit 3 outputs record data. The record data is supplied to a head H. The head H records the record data on a magnetic tape T. Normally, the head H is constructed of a plurality of rotating heads. With the rotating heads, record data of each frame is recorded on corresponding tracks of the magnetic tape T.
Reproduction data retrieved from the magnetic tape T through the head H is supplied to a reproduction processing circuit 4. The reproduction processing circuit performs various predetermined processes such as channel demodulating process, frame desegmenting process, error correction code decoding process, block code decoding process, and block desegmenting process. The reproduction video data is supplied to the digital output terminal ODa. In addition, the reproduction video data is supplied to a D/A converter 5. The D/A converter 5 outputs an analog reproduction video signal. The analog reproduction video signal is supplied to the output terminal OAa. The digital VTR 1A also has a timing control circuit 6 that controls timing of the recording process and reproducing process. The timing control circuit 6 generates for example a clock CK1 for use with the A/D converter 2.
As with the VTR 1A, the other digital VTR 1B has an A/D converter 12, a record processing circuit 13, a head H, a reproduction processing circuit 14, a D/A converter 15, and a timing control circuit 16. The timing control circuit 16 generates a clock CK2 for use with the A/D converter 12.
With reference to FIG. 5, an analog video unit 10 is disposed between the digital VTRs 1A and 1B. The analog video unit 10 processes an analog video signal. The analog video unit 10 processes a reproduction analog video signal of the digital VTR 1A. The digital VTR 1B records the output signal of the analog video unit 10. In this system, the A/D converter 2 of the digital VTR 1A should digitize an analog video signal. In addition, the A/D converter 12 of the digital VTR 1B should digitize the analog video signal.
Generally, the digital VTRs 1A and 1B asynchronously operate with each other. In the A/D converting processes of these VTRs 1A and 1B, the phase of the sampling clock CK1 does not accord with the phase of the sampling clock CK2. FIG. 6 shows the difference of phases of the sampling clocks CK1 and CK2. For the block encoding process in the record processing circuit 3, n x m blocks BL1, BL2, BL3, . . . , and so forth are formed (where m=4 in FIG. 6). The analog video unit 10 supplies a video signal Sv to the digital VTR 1B. The value of each pixel is encoded with one bit by block encoding process such as ADRC process. Each block of the video signal Sv where one-bit data is decoded has two values that range from 0 to 255. For example, for block BL1, values 50 and 70 are decoded. For block BL2, values 120 and 140 are decoded.
When the digital VTR 1B records the video signal Sv, since the phase of the clock CK1 does not accord with the phase of the clock CK2, the block segmentation performed in the digital VTR 1A differs from the block segmentation performed in the digital VTR 1B. In FIG. 6, when the A/D conversion is performed with the clock CK2 represented by dotted lines, due to the phase difference of the clocks, adjacent block data (with a value 120) is contained in data of block BL1. In other words, pixels of the block BL1 have values 50, 70, 50, 120, . . . and so forth.
Thus, when the ADRC decoding process is performed in the digital VTR 2 so as to perform edge matching for one bit (namely, decoded values of the maximum value and minimum value of the block take place), the decoded values of the pixels of the block BL1 are 50, 50, 50, and 120. Thus, a distortion where the second decoded value is changed from 70 to 50 takes place. In other words, the phase difference of the clocks causes one pixel to be shifted. Consequently, the block construction of the digital VTR 1A differs from that of the digital VTR 1B, thereby degrading the image quality.
When a time axis deviation takes place in the analog video unit 10 shown in FIG. 5, a plurality of pixels instead of one pixel may be shifted at each block boundary. In the digital VTR, while the horizontal synchronous signal and the vertical synchronous signal contained in the video signal are not recorded, the reproduction signal is D/A converted. After the reproduction signal has been D/A converted, such synchronous signals are added to the analog signal. Since the reproduction data Contains a time-axis-fluctuating component, which is referred to as a jitter, the relative positions between the synchronous signals and the data may vary. Thus, several pixels may be shifted.
Thus, as shown in FIG. 5, in the dubbing system that temporarily converts a digital video signal into an analog video signal, each block boundary is shifted for one to several pixels, thereby deteriorating the image quality.
Likewise, such a problem takes place when a digital video signal is not converted into an analog video signal (namely, the dubbing is performed with a digital signal). FIG. 7 shows a system constructed of digital VTRs 1A, 1B, and 1C and an edit processing unit 11. The edit processing unit 11 combines a digital video signal SA that is supplied from a digital output terminal ODa of the digital VTR 1A with a part of a digital video signal SB that is supplied from an output terminal ODb of the digital VTR 1B. The edit processing unit 11 outputs a digital video signal SC. The digital video signal SC is supplied to a digital input terminal IDc of the digital VTR 1C. The digital VTR 1C performs a recording process for the combined digital video signal SC and then records the signal on a tape.
FIGS. 8A, 8B, and 8C show some examples of the combining process performed by the edit processing unit 11. In FIGS. 8A, 8B, and 8C, portions represented by dotted lines are extracted from the digital video signal SA. The extracted portions are positioned in the digital video signals. In any process shown in FIGS. 8A, 8B, and 8C, the boundary of an image being extracted do not always accord with the boundary of a block. In other words, in most cases, they do not match each other. The edit processing unit 11 extracts image portion from an editing point of view rather than considering blocks for block encoding process.
FIG. 9 shows a block construction that changes in the editing process shown in FIG. 8A. When a portion represented by a dotted line is extracted from the digital video signal SA, portions of blocks B1, B2, Bn, and Bn+l that are disposed at the upper left corner of the digital image signal SA are contained in a new block B1' (represented by a dotted line) as shown in FIG. 10A.
FIG. 10A is an example of a block that is constructed of 4.times.4 pixels. This block contains data of original blocks B1, B2, Bn, and Bn+1, each of which is constructed of 2.times.2 pixels. A numeral of each pixel position represents the value thereof. The digital VTR 1C connected to the edit processing unit 11 encodes a new block with one-bit ADRC process. In other words, the maximum value of the new block is 150, whereas the minimum value of the new block is 40. Thus, as shown in FIG. 10B, with a threshold value of 95, encoded data 1 and 0 are formed.
When data that has been encoded in such a way and recorded on a tape is decoded by edge matching technique, encoded data "1" and "0" are treated as values "150" and "40", respectively. FIG. 10C shows decoded values of the block B1'. As is clear from FIGS. 10A and 10B, the decoded values remarkably vary and a distortion takes place.
As described above, since the phase difference takes place in the A/D conversion or the boundary of an image extracted does not accord with the boundary of a block, when dubbing is performed, the image is deteriorated. Due to the phase difference in the A/D conversion, the beginning edge of a block is horizontally shifted. On the other hand, due to the disaccordance of the boundary of the extracted image and the boundary of the block, the beginning edge may be shifted horizontally and vertically.
When the beginning edge of a block of a reproducing VTR accords with the beginning edge of a block of a recording VTR, if other noises are ignored, no image deterioration takes place. Even if other noises such as quantizing noise and surrounding noise are considered, the image deterioration in the case of the accordance of the beginning edge of a block is lesser than that in the case of the disaccordance thereof.